Study of trigger instabilities in smart power technology ESD protection devices using a laser interferometric thermal mapping technique

Trigger dynamics during a single ESD event and pulse-to-pulse variations in the trigger location are studied in ESD protection devices of a smart power technology. NPN bipolar transistors with and without a lateral shift in the collector buried layer are investigated. The homogeneity of the current flow along the device width is studied by means of a laser interferometric thermal mapping technique. The investigations are performed as a function of device type, pulse duration and stress magnitude. The trigger behavior is correlated with the time evolution of holding voltage, shape of the high current IV curves, and results of failure analysis. A model for thermally - driven current flow dynamics is proposed and the failure mechanism is explained in terms of the observed thermal behavior.

[1]  Charvaka Duvvury,et al.  Electrothermal simulation of electrical overstress in advanced nMOS ESD I/O protection devices , 1993, Proceedings of IEEE International Electron Devices Meeting.

[3]  G. Reimbold,et al.  Study of a 3D phenomenon during ESD stresses in deep submicron CMOS technologies using photon emission tool , 1997, 1997 IEEE International Reliability Physics Symposium Proceedings. 35th Annual.

[4]  M. Stecher,et al.  Wide range control of the sustaining voltage of ESD protection elements realized in a smart power technology , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[5]  W. Fichtner,et al.  Analysis and compact modeling of lateral DMOS power devices under ESD stress conditions , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[6]  V. F. Sinkevitch,et al.  Electrical instability and filamentation in ggMOS protection structures , 1997 .

[7]  C. Musshoff,et al.  Does The Esd-failure Current Obtained By Transmissionline Pulsing Always Correlate To Human Body Model Tests? , 1997 .

[8]  Dionyz Pogany,et al.  Study of triggering inhomogeneities in gg-nMOS ESD protection devices via thermal mapping using backside laser interferometry , 2000 .

[9]  Eckehard Schöll,et al.  Nonequilibrium phase transitions in semiconductors , 1987 .

[10]  D. S. Campbell,et al.  Thermal failure in semiconductor devices , 1990 .

[11]  C. Duvvury,et al.  Achieving uniform nMOS device power distribution for sub-micron ESD reliability , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[12]  Dionyz Pogany,et al.  Thermal and free carrier concentration mapping during ESD event in smart Power ESD protection devices using an improved laser interferometric technique , 2000 .

[13]  X. Guggenmos,et al.  Does The Esd-failure Current Obtained By Transmissionline Pulsing Always Correlate To Human Body Model Tests? , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[14]  D. H. Pontius,et al.  Second breakdown and damage in junction devices , 1973 .

[15]  A. Amerasekera,et al.  Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[16]  M. Stecher,et al.  Interferometric temperature mapping during ESD stress and failure analysis of smart power technology ESD protection devices , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[17]  S. Ramaswamy,et al.  A unified substrate current model for weak and strong impact ionization in sub-0.25 /spl mu/m NMOS devices , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[18]  E. A. Amerasekera,et al.  ESD in silicon integrated circuits , 1995 .

[19]  G. K. Wachutka Analytical Model for the Destruction Mechanism of GTO-Like Devices by Avalanche Injection , 1989 .

[20]  Guido Groeseneken,et al.  Non-uniform triggering of gg-nMOSt investigated by combined emission microscopy and transmission line pulsing , 1999 .

[21]  G. Krieger,et al.  Thermal response of integrated circuit input devices to an electrostatic energy pulse , 1987, IEEE Transactions on Electron Devices.

[22]  W. Fichtner,et al.  Characterization and optimization of a bipolar ESD-device by measurements and simulations , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[23]  Dionyz Pogany,et al.  Simulation and experimental study of temperature distribution during ESD stress in smart-power technology ESD protection structures , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[24]  Horst Gieser,et al.  RISETIME EFFECTS OF HBM AND SQUARE PULSES TRANSISTORS ON THE FAILURE THRESHOLDS OF GGNMOS , 1996 .

[25]  Amitava Chatterjee,et al.  Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow , 1992 .

[26]  K. Mckay Avalanche Breakdown in Silicon , 1954 .