论文信息 - Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices

Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices — Technology directions

3D integration technology using thin die and Through-Silicon-Via, TSV, connections affect transistor and circuit behavior through electrical, mechanical and thermal interactions. The roadmap for further 3D technology development should focus on minimizing these effects.

Eric Beyne | E. Beyne

[1] Chukwudi Okoro,et al. Thermo-Mechanical Characterization of Copper Through-Silicon-Via Interconnect for 3D Chip Stacking (Thermo-mechanische karakterisatie van koper via interconnecties doorheen silicium voor 3D opeenstapeling van chips) , 2010 .

[2] Suk-kyu Ryu,et al. Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects , 2011, IEEE Transactions on Device and Materials Reliability.

[3] Bart Vandevelde,et al. Impact of the electrodeposition chemistry used for TSV filling on the microstructural and thermo-mechanical response of Cu , 2011 .

[4] Luca Benini,et al. Design Issues and Considerations for Low-Cost 3-D TSV IC Technology , 2010, IEEE Journal of Solid-State Circuits.

[5] Bart Vandevelde,et al. Cu pumping in TSVs: Effect of pre-CMP thermal budget , 2011, Microelectron. Reliab..

[6] Charles S. Smith. Piezoresistance Effect in Germanium and Silicon , 1954 .