Inspection Challenges with Broadba

With the continuous shrink of tec lithography becomes more and more challeng node, double patterning technology (DPT) was t achieving the fine device structures. Until EUV i high volume manufacturing (HVM) solution, patterning technology (TPT) will be required to However, as the industry goes forward with sca nm nodes the chip manufacturers are anticip four masks per layer. Exposing the patterns se the spacing or pitch of the structures to be redu of two (or more for triple/quadruple pat increasing the metrology and inspection challeng As with many of the previous geometry shr be the usual concerns about yield and reliabili control and predict yield for sub-14 nm nodes design information when integrated with inspec can help predict design weak spots efficiently. It of this paper to elucidate some of the inspection solutions for sub 14nm device structures.