Atomistic approach to variability of bias-temperature instability in circuit simulations

A blueprint for an atomistic approach to introducing time-dependent variability into a circuit simulator in a realistic manner is demonstrated. The approach is based on previously proven physics of stochastic properties of individual gate oxide defects and their impact on FET operation. The proposed framework is capable of following defects with widely distributed time scales (from fast to quasi-permanent), thus seamlessly integrating random telegraph noise (RTN) effects with bias temperature instability (BTI). The use of industry-standard circuit simulation tools allows for studying realistic workloads and the interplay of degradation of multiple FETs.

[1]  Yu Cao,et al.  The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  T. Grasser,et al.  Time-dependent defect spectroscopy for characterization of border traps in metal-oxide-semiconductor transistors , 2010 .

[3]  Sachin S. Sapatnekar,et al.  NBTI-Aware Synthesis of Digital Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[4]  W. Marsden.  I and J , 2012 .

[5]  Paul Zuber,et al.  Variability aware modeling of SoCs: From device variations to manufactured system yield , 2009, 2009 10th International Symposium on Quality Electronic Design.

[6]  T. Grasser,et al.  The statistical analysis of individual defects constituting NBTI and its implications for modeling DC- and AC-stress , 2010, 2010 IEEE International Reliability Physics Symposium.

[7]  A. Asenov,et al.  Statistical NBTI-effect prediction for ULSI circuits , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[8]  M. Nafría,et al.  Probabilistic defect occupancy model for NBTI , 2011, 2011 International Reliability Physics Symposium.

[9]  A. Visconti,et al.  Comprehensive Analysis of Random Telegraph Noise Instability and Its Scaling in Deca–Nanometer Flash Memories , 2009, IEEE Transactions on Electron Devices.

[10]  B. Kaczer,et al.  Recent advances in understanding the bias temperature instability , 2010, 2010 International Electron Devices Meeting.

[11]  T. Ragheb,et al.  An extensive and improved circuit simulation methodology for NBTI recovery , 2010, 2010 IEEE International Reliability Physics Symposium.

[12]  R. Degraeve,et al.  Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[13]  T. Grasser,et al.  The time dependent defect spectroscopy (TDDS) for the characterization of the bias temperature instability , 2010, 2010 IEEE International Reliability Physics Symposium.

[14]  Nicolas Planes,et al.  Managing SRAM reliability from bitcell to library level , 2010, 2010 IEEE International Reliability Physics Symposium.

[15]  N. Horiguchi,et al.  Response of a single trap to AC negative Bias Temperature stress , 2011, 2011 International Reliability Physics Symposium.

[16]  Andrew R. Brown,et al.  RTS amplitudes in decananometer MOSFETs: 3-D simulation study , 2003 .

[17]  李幼升,et al.  Ph , 1989 .