Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size
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T. Hong | P. Sung | K. Kao | G. Luo | Y. Lee | T. Chao | W. Wu | Y. Wang | Y. Li | S. Samukawa | S. Chang | J. Tarng | Chien-Hsueh Chiang | Y.-S. Yang | S. Kola | W. Chang | W. C. Ma | Ta-Chun Cho | Min-Hui Chuang | C. Su | Pei-Hsuan Wu | C. Wu | M. Chiang | W.-H. Lu | J. Lin | X.-R. Yu | C.-Y. Yang | W.-J. Chen | T.-C. Sun | Yun Da | T. Maeda