과학기술위성 3호 온보드 컴퓨터의 양성자 빔에 의한 Single Event Effect 분석

Field Programmable Gate Array(FPGA)s are replacing traditional integrated circuits for space applications due to their lower development cost as well as reconfigurability. However, they are very sensitive to single event upset (SEU) caused by space radiation environment. In order to mitigate the SEU, on-board computer of STSAT-3 employed a triple modular redundancy(TMR) and scrubbing scheme. Experimental results showed that upset threshold energy was improved from 10.6 MeV to 20.3 MeV when the TMR and the scrubbing were applied to the on-board computer. Combining the experimental results with the orbit simulation results, calculated bit-flip rate of on-board computer is 1.23 bit-flips/day assuming in the worst case of STSAT-3 orbit.