High-throughput one-dimensional median and weighted median filters on FPGA

Most effort in designing median filters has focused on two-dimensional filters with small window sizes, used for image processing. However, recent work on novel image processing algorithms, such as the Trace transform, has highlighted the need for architectures that can compute the median and weighted median of large one-dimensional windows, to which the optimisations in the aforementioned architectures do not apply. A set of architectures for computing both the median and weighted median of large, flexibly sized windows through parallel cumulative histogram construction is presented. The architecture uses embedded memories to control the highly parallel bank of histogram nodes, and can implicitly determine window sizes for median and weighted median calculations. The architecture is shown to perform at 72 Msamples, and has been integrated within a Trace transform architecture.

[1]  Liang-Gee Chen,et al.  VLSI implementation of a selective median filter , 1996 .

[2]  Martin Fleury,et al.  Two-dimensional median filter algorithm for parallel reconfigurable computers , 1995 .

[3]  Alexander Kadyrov,et al.  The Trace Transform and Its Applications , 2001, IEEE Trans. Pattern Anal. Mach. Intell..

[4]  Vincenzo Piuri,et al.  Digital Median Filters , 2002, J. VLSI Signal Process..

[5]  Wayne Luk,et al.  An integrated system for developing regular array designs , 2001, Journal of systems architecture.

[6]  Jun-Dong Cho,et al.  A fast VLSI implementation of sorting algorithm for standard median filters , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[7]  Dana S. Richards,et al.  VLSI median filters , 1990, IEEE Trans. Acoust. Speech Signal Process..

[8]  Lukás Sekanina,et al.  Novel Hardware Implementation of Adaptive Median Filters , 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

[9]  Levent Onural,et al.  Design and implementation of a general-purpose median filter unit in CMOS VLSI , 1990 .

[10]  S. Nooshabadi,et al.  FPGA implementation of a median filter , 1997, TENCON '97 Brisbane - Australia. Proceedings of IEEE TENCON '97. IEEE Region 10 Annual Conference. Speech and Image Technologies for Computing and Telecommunications (Cat. No.97CH36162).

[11]  Juan A. Gómez-Pulido,et al.  AN FPGA-BASED IMPLEMENTATION FOR MEDIAN FILTER MEETING THE REAL-TIME REQUIREMENTS OF AUTOMATED VISUAL INSPECTION SYSTEMS , 2002 .

[12]  Christos-Savvas Bouganis,et al.  Efficient Realtime FPGA Implementation of the Trace Transform , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[13]  Christos-Savvas Bouganis,et al.  Real-time hardware acceleration of the trace transform , 2007, Journal of Real-Time Image Processing.

[14]  I. Chakrabarti,et al.  High Throughput VLSI Architecture for One Dimensional Median Filter , 2008, 2008 International Conference on Signal Processing, Communications and Networking.

[15]  Wayne Luk,et al.  Novel FPGA-based implementation of median and weighted median filters for image processing , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[16]  Danny Crookes,et al.  Design and implementation of a novel algorithm for general purpose median filtering on FPGAs , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[17]  Jarmo Takala,et al.  VLSI-efficient implementation of full adder-based median filter , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[18]  Wayne Luk,et al.  Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective , 2007, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP).

[19]  A.M. Alsuwailem,et al.  A new approach for real-time histogram equalization using FPGA , 2005, 2005 International Symposium on Intelligent Signal Processing and Communication Systems.