Développement de circuits logiques programmables résistants aux aléas logiques en technologie CMOS submicrométrique

L'electronique associee aux detecteurs de particules du grand collisionneur d'hadrons (LHC), en construction au CERN, fonctionnera dans un environnement tres radioactif. La plupart des composants microelectroniques developpes pour la premiere generation des experiences du LHC ont ete concues avec des buts specifiques et tres precis, non adaptables pour d'autres applications. Les composants commerciaux ne peuvent pas etre employes en proximite du point de collision des particules, car ils ne sont pas tolerants aux radiations. Cette these contribue a couvrir le besoin en composants programmables resistants aux rayonnements et aux alea logiques pour les experiences de physique des hautes energies. Dans ce sens, deux composants sont en cours de developpement : un dispositif logique programmable (PLD) et un reseau de portes programmables in-situ (FPGA). Ce travail s'est concentre egalement sur la recherche d'un registre resistant aux alea logiques dans les deux technologies mentionnees. Le registre est utilise comme bascule pour les donnees d'utilisateur dans le FPGA et le PLD, mais aussi comme cellule de configuration dans le FPGA.

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