Design of high power-addecd efficiency FET amplifiers operating with very low drain bias voltages for use in mobile telephones at 1.7 GHz

Two single-stage GaAs class F power amplifiers with very high efficiency at low drain bias voltages have been designed and tested at 1.7 GHz. The first power amplifier was designed to achieve maximum power-added efficiency while the second power amplifier design realizes the best compromise between output power and power-added efficiency. At Vds=3V, the measured output power of the first amplifier is l9dBm with a power-added efficiency of 73%. The output power of the second amplifier (also biased at Vds=3V) is 24dBm with a power-added efficiency of 70%. These results were achieved by using suitable terminations for the second and third harmonics. In our knowledge, the obtained results present the state of the art published for low voltage bias conditions.