Formal Design and Synthesis of GALS Architectures

A Globally Asynchronous and Locally Synchronous (GALS) system can be obtained by: (1) integrating independently clocked domains via an asynchronous communication link or, (2) desynchronising a synchronous system into a number of synchronous compartments whose interface is seamlessly refined to handle asynchronous communication. In the area of system integration, a number of schemes have been proposed to handle the synchronisation problem. There have been no comparative performance analysis to aid the designer to choose one scheme over another. Therefore, we classify these schemes into three generic categories so that they can be brought to a common platform for comparison and show how they can be applied to an existing partitioned synchronous architecture to obtain a reliable, low latency and efficient clock control architecture. We present circuit solutions and comparative analysis results for the generic classes in terms of circuit implementation, performance and relative power consumption. The various system desynchronisation methodologies proposed are targeted for single clock synchronous systems where all components operate on the same