Statistical characterization of current paths in narrow poly-Si channels
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R. Degraeve | B. Kaczer | J. Van Houdt | G. Van den bosch | G. Groeseneken | M. Toledano-Luque | G. Kar | R. Degraeve | B. Kaczer | G. Groeseneken | M. Toledano-Luque | P. Roussel | J. van Houdt | A. Arreghini | G. Van den bosch | G. S. Kar | B. Tang | A. Suhane | Ph. Roussel | A. Suhane | B. Tang | A Arreghini
[1] Shinsugita-cho Isogo-ku,et al. Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory , 2007 .
[2] T. Grasser,et al. Statistics of Multiple Trapped Charges in the Gate Oxide of Deeply Scaled MOSFET Devices—Application to NBTI , 2010, IEEE Electron Device Letters.
[3] L. Breuil,et al. Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology , 2011, 2011 3rd IEEE International Memory Workshop (IMW).