ROAdNoC: runtime observability for an adaptive network on chip architecture
暂无分享,去创建一个
[1] William J. Dally,et al. Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.
[2] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[3] Kees G. W. Goossens,et al. Congestion-Controlled Best-Effort Communication for Networks-on-Chip , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[4] Shekhar Y. Borkar,et al. Thousand Core ChipsA Technology Perspective , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[5] Jorg Henkel,et al. Run-time adaptive on-chip communication scheme , 2007, ICCAD 2007.
[6] Li-Shiuan Peh,et al. Design-space exploration of power-aware on/off interconnection networks , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..
[7] Wolfgang Karl,et al. SCI Monitoring Hardware and Software: Supporting Performance Evaluation and Debugging , 1999, Scalable Coherent Interface.
[8] Henry Hoffmann,et al. On-Chip Interconnection Architecture of the Tile Processor , 2007, IEEE Micro.
[9] Ken Mai,et al. The future of wires , 2001, Proc. IEEE.
[10] Kees G. W. Goossens,et al. An event-based monitoring service for networks on chip , 2005, TODE.
[11] Diederik Verkest,et al. Operating-system controlled network on chip , 2004, Proceedings. 41st Design Automation Conference, 2004..
[12] Jörg Henkel,et al. ADAM: Run-time agent-based distributed application mapping for on-chip communication , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[13] Radu Marculescu,et al. Application-specific network-on-chip architecture customization via long-range link insertion , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[14] William J. Dally,et al. Research Challenges for On-Chip Interconnection Networks , 2007, IEEE Micro.
[15] Ali Ahmadinia,et al. Dynamic interconnection of reconfigurable modules on reconfigurable devices , 2005, IEEE Design & Test of Computers.
[16] Stamatis Vassiliadis,et al. FLUX Networks: Interconnects on Demand , 2006, 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.
[17] Sriram R. Vangal,et al. A 5-GHz Mesh Interconnect for a Teraflops Processor , 2007, IEEE Micro.