RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder

In this brief, we propose a fast yet energy-efficient reconfigurable approximate carry look-ahead adder (RAP-CLA). This adder has the ability of switching between the approximate and exact operating modes making it suitable for both error-resilient and exact applications. The structure, which is more area and power efficient than state-of-the-art reconfigurable approximate adders, is achieved by some modifications to the conventional carry look ahead adder (CLA). The efficacy of the proposed RAP-CLA adder is evaluated by comparing its characteristics to those of two state-of-the-art reconfigurable approximate adders as well as the conventional (exact) CLA in a 15 nm FinFET technology. The results reveal that, in the approximate operating mode, the proposed 32-bit adder provides up to 55% and 28% delay and power reductions compared to those of the exact CLA, respectively, at the cost of up to 35.16% error rate. It also provides up to 49% and 19% lower delay and power consumption, respectively, compared to other approximate adders considered in this brief. Finally, the effectiveness of the proposed adder on two image processing applications of smoothing and sharpening is demonstrated.

[1]  Sandeep K. Gupta,et al.  A Re-design Technique for Datapath Modules in Error Tolerant Applications , 2008, 2008 17th Asian Test Symposium.

[2]  Caro Lucas,et al.  Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Paolo Ienne,et al.  Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design , 2008, 2008 Design, Automation and Test in Europe.

[4]  Mark S. K. Lau,et al.  Energy-aware probabilistic multiplier: design and analysis , 2009, CASES '09.

[5]  Peng Li,et al.  Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Fabrizio Lombardi,et al.  New Metrics for the Reliability of Approximate and Probabilistic Adders , 2013, IEEE Transactions on Computers.

[7]  Kaushik Roy,et al.  Low-Power Digital Signal Processing Using Approximate Adders , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Weikang Qian,et al.  A new approximate adder with low relative error and correct sign calculation , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[9]  Basant K. Mohanty,et al.  Area–Delay–Power Efficient Carry-Select Adder , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Rakesh Kumar,et al.  On reconfiguration-oriented approximate adder design and its application , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[11]  Arnab Raha,et al.  Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Muhammad Shafique,et al.  A low latency generic accuracy configurable adder , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[13]  Yiorgos Tsiatouhas,et al.  New High-Speed Multioutput Carry Look-Ahead Adders , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  Arthur Robert Weeks,et al.  The Pocket Handbook of Image Processing Algorithms In C , 1993 .

[15]  Ahmed M. Eltawil,et al.  Equi-Noise: A Statistical Model That Combines Embedded Memory Failures and Channel Noise , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Zhi-Hui Kong,et al.  Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Andrew B. Kahng,et al.  Accuracy-configurable adder for approximate arithmetic designs , 2012, DAC Design Automation Conference 2012.

[18]  Gang Wang,et al.  Enhanced low-power high-speed adder for error-tolerant application , 2009, 2010 International SoC Design Conference.