Long lossy lines (L/sup 3/) and their impact upon large chip performance
暂无分享,去创建一个
[1] Robert H. Dennard,et al. Modeling and characterization of long on-chip interconnections for high-performance microprocessors , 1995, IBM Journal of Research and Development.
[2] Christopher Henry Bajorek,et al. The thin-film module as a high-performance semiconductor package , 1982 .
[3] W. V. Vilkelis. Lead reduction among combinatorial logic circuit , 1982 .
[4] Jason Cong,et al. The new line in IC design , 1997 .
[5] Leon L. Wu,et al. Physical and electrical design features of the IBM Enterprise System/9000 circuit module , 1992, IBM J. Res. Dev..
[6] J. P. Krusius,et al. Packaging alternatives to large silicon chips: tiled silicon on MCM and PWB substrates , 1996 .
[7] G. A. Sai-Halasz,et al. Performance trends in high-end processors , 1995, Proc. IEEE.
[8] S. Tam,et al. Package clock distribution design optimization for high-speed and low-power VLSIs , 1997 .
[9] T.H. Lee,et al. A 600 MHz superscalar RISC microprocessor with out-of-order execution , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.