POWER LATERAL DMOS TRANSISTOR TEST STRU

This work is aimed at the design and the fabrication of LDMOS test structures for showing the impact of cell dimensions and epilayer properties on the device characteristics and to optimize the VB~bN tradeoff. The influence of the device layout, edge device termination and geometrical dimensions is investigated with these test smctures. Square, circular, single-finger, multi-finger and waved gate layouts are considered in the test monitor chip. The fabrication process is a conventional poly-gate DMOS process based on a double diffusion for the active channel formation. In addition, the resurfed LDMOS physical behaviour is analyzed by means of 2D simulations, and the results obtained are compared with that obtained from the experimental data