A 1.5 V CMOS balanced differential switched-capacitor filter with internal clock boosters

A 1.5 V SC filter employing a balanced differential structure and a internal clock booster is proposed. The design technique is demonstrated by a fourth-order bandpass biquad filter fabricated with a standard 0.8 /spl mu/m CMOS technology. This prototype fourth-order filter which has a center frequency of 8 kHz and a clock frequency of 400 kHz dissipates about 330 /spl mu/W with a 1.5 V power supply. Including the clock generator and boosters, it occupies 600/spl times/1500 /spl mu/m/sup 2/. The measurement result shows this filter has the IMD of 0.1 percent for 1.2 V/sub IP/ differential signal.

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