Predictive State-Space for on-Chip Crosstalk Noise

Decreasing feature sizes to deep sub-micrometer (DSM) dimensions offers a large number of advantages for electronic devices such as high functional integration, reduced size and improvement in performance. However, designing at the DSM level brought with it challenges to -among others -crosstalk and delay techniques. The use of high clock frequencies, coupled with a large number of longer interconnect wires -of small cross section -packed closer together, gives rise to significant inductive coupling between on-chip interconnects. Therefore, for accurate modelling of crosstalk noise, the inductive and distributed nature of on-chip interconnects have to be properly modelled. In this paper, a state-space-based analytical model for crosstalk noise estimation is presented. The model can also assist in predicting the effect of crosstalk on circuit parameters.

[1]  S. Wong,et al.  On-chip inductance modeling of VLSI interconnects , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[2]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Lawrence T. Pileggi,et al.  The Elmore Delay as a Bound for RC Trees with Generalized Input Signals , 1995, 32nd Design Automation Conference.

[4]  L.M. Coulibaly,et al.  Analytical ramp delay model for distributed on-chip RLC interconnects , 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

[5]  Lawrence T. Pileggi,et al.  The Elmore delay as a bound for RC trees with generalized input signals , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Kaustav Banerjee,et al.  Analysis of on-chip inductance effects for distributed RLC interconnects , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Ernest S. Kuh,et al.  Exact moment matching model of transmission lines and application to interconnect delay estimation , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[8]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[9]  Jun Chen,et al.  Worst case crosstalk noise for nonswitching victims in high-speed buses , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Guoqing Chen,et al.  An RLC interconnect model based on fourier analysis , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  L.M. Coulibaly,et al.  A Comparative Analysis of a Distributed On-Chip RLC Interconnect Model under Ramp Excitation , 2005, EUROCON 2005 - The International Conference on "Computer as a Tool".

[13]  H. J. Kadim,et al.  Analytical crosstalk noise and its induced-delay estimation for distributed RLC interconnects under ramp excitation , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[14]  Takayasu Sakurai,et al.  Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .

[15]  T. Sakurai,et al.  Simple formulas for two- and three-dimensional capacitances , 1983, IEEE Transactions on Electron Devices.