LEAKAGE AND VARIATION AWARE THERMAL MANAGEMENT OF NANOMETER SCALE ICS

For sub-100 nm CMOS technologies, leakage power forms a significant component of the total power dissipation, especially due to within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). Since leakage power and operating temperature are electrothermally coupled to each other, increasing power dissipation and thermal problems are becoming key concerns not only from a thermal management point of view but also because most reliability mechanisms are highly temperature sensitive. This paper provides an overview of a novel methodology for making temperature and reliability aware power/performance/cooling-cost tradeoffs in leakage dominant nanometer scale high-performance ICs. First, a framework to accurately estimate subthreshold leakage under both within-die and die-to-die parameter variations is outlined. It is shown that die-to-die temperature variations can significantly increase leakage power, mainly because of electrothermal couplings between power and temperature. Next, a recently developed self-consistent electrothermal methodology to accurately estimate the junction temperature is presented and is shown to be significant for thermal management of leakage and variation dominant CMOS technologies. The methodology is then applied to provide a reliability and thermally aware design space that can be used to optimize and compare various designs.

[1]  T. Sakurai,et al.  Optimization of V/sub DD/ and V/sub TH/ for low-power and high-speed applications , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[2]  K. Olasupo,et al.  Time dependent breakdown of ultrathin gate oxide , 2000 .

[3]  K. Banerjee,et al.  Impact of off-state leakage current on electromigration design rules for nanometer scale CMOS technologies , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[4]  Kaustav Banerjee,et al.  Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era , 2004, Proceedings. 41st Design Automation Conference, 2004..

[5]  I. Aller,et al.  CMOS circuit technology for sub-ambient temperature operation , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[6]  P.P. Gelsinger,et al.  Microprocessors for the new millennium: Challenges, opportunities, and new frontiers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[7]  Ravi Mahajan,et al.  The Evolution of Microprocessor Packaging , 2000 .

[8]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[9]  Stephen H. Gunther,et al.  Managing the Impact of Increasing Microprocessor Power Consumption , 2001 .

[10]  B. Agarwala,et al.  Scaling effect on electromigration in on-chip Cu wiring , 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

[11]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[12]  Vivek De,et al.  Technology and design challenges for low power and high performance [microprocessors] , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[13]  R. Viswanath.  Thermal Performance Challenges from Silicon to Systems , 2000 .

[14]  Shekhar Borkar,et al.  Low power design challenges for the decade , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[15]  J. Black,et al.  Electromigration—A brief survey and some recent results , 1969 .

[16]  Ishiuchi,et al.  Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas , 2004 .

[17]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[18]  Sheng-Chih Lin,et al.  A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management , 2003, IEEE International Electron Devices Meeting 2003.

[19]  Kaustav Banerjee,et al.  Subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).