Exploring area and total wirelength using a cell merging technique

The industry of Integrated Circuits (ICs) has been making increasingly complex chips with up to billions of transistors in a single die. As we cannot do the design flow by hand, the leading adopted solution to deal with this challenge has been to use a pre-designed library of standard cells and using EDA tools to automate the process. Nevertheless, the resulting netlist is not as efficient in terms of the number of transistors as a handmade design, possibly reflecting in the overall area, power, and delay of the circuit. To generate cells on-demand is a way to improve this inherent limitation, as previous works demonstrate. In this paper, we investigate a netlist optimization methodology based on gate merging and its impacts regarding area and wire-length when applied to the Nagate’s Open Cell Library for 45nm. We obtained a reduction in area and total wire-length of 3.5% and 4.2% on average, respectively.

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