Reconfiguration of high performance VLSI sub-arrays

Reconfigurable techniques attempt to realise maximum possible fault-free sub-arrays in mesh connected VLSI arrays with faulty elements. Although this problem has been investigated extensively, the performance of the resulting sub-arrays has not been addressed fully. In this paper, techniques for finding the high performance target array (HPTA) in the given VLSI array are proposed. First, it is shown that finding an HPTA in the given VLSI array is equivalent to solving a typical optimisation problem of multistage decision. Then a heuristic algorithm is presented based on dynamic programming for an HPTA. The proposed algorithm minimises the interconnect length of the target array by revising each original logical column to the optimal one without sacrificing on the size of the sub-array. Simulation results conclusively show that the proposed algorithm reduces the number of long interconnects in the sub-array without loss of harvest.

[1]  M. Bohr.  Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.

[2]  Sudhakar M. Reddy,et al.  On the Repair of Redundant RAMs , 1989, 26th ACM/IEEE Design Automation Conference.

[3]  Eby G. Friedman,et al.  Optimum wire sizing of RLC interconnect with repeaters , 2004, Integr..

[4]  Chor Ping Low,et al.  An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays , 2000, IEEE Trans. Computers.

[5]  Wu Jigang,et al.  A run-time reconfiguration algorithm for VLSI arrays , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[6]  Clement W. H. Lam,et al.  A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays , 1989, IEEE Trans. Computers.

[7]  Li Zhang,et al.  Fault-Tolerant Meshes with Small Degree , 2002, IEEE Trans. Computers.

[8]  Wu Jigang,et al.  An improved reconfiguration algorithm for degradable VLSI/WSI arrays , 2003, J. Syst. Archit..

[9]  Chin-Long Wey,et al.  On the Repair of Redundant RAM's , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Takayasu Sakurai,et al.  Power distribution analysis of VLSI interconnects using model orderreduction , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Mariagiovanna Sami,et al.  Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays , 1989 .

[12]  J. S. Neely,et al.  Interconnect and circuit modeling techniques for full-chip power supply noise analysis , 1998 .

[13]  Jason Cong,et al.  Optimal wiresizing under Elmore delay model , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Hon Wai Leong,et al.  On the reconfiguration of degradable VLSI/WSI arrays , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Itsuo Takanami,et al.  Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions , 2000, IEEE Trans. Computers.

[16]  Shambhu J. Upadhyaya,et al.  A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors , 1997, IEEE Trans. Computers.

[17]  M. Swaminathan,et al.  Modeling of power supply noise in large chips with nonlinear circuits , 2002, Electrical Performance of Electronic Packaging,.

[18]  Wu Jigang,et al.  New Architecture and Algorithms for Degradable VLSI/WSI Arrays , 2002, COCOON.

[19]  K. Sawa,et al.  Effect of arc behavior on material transfer: a review , 1996, Electrical Contacts - 1996. Proceedings of the Forty-Second IEEE Holm Conference on Electrical Contacts. Joint with the 18th International Conference on Electrical Contacts.

[20]  Sy-Yen Kuo,et al.  Efficient reconfiguration algorithms for degradable VLSI/WSI arrays , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Alfred V. Aho,et al.  The Design and Analysis of Computer Algorithms , 1974 .