An Embedded RISC Core Performance for ATM Network Interface Processing

Abstract The use of an embedded reduced instruction set computer (RISC) as a processing core for an ATM network interface can provide such interface with very useful features, such as simplicity of interface design, short developing cycle, and reduced cost of development. In addition, it provides scalability where such core could support the processing requirements by ATM interface to deliver different high-speed data transmission, which the user-network ATM interface protocol recommends. This article describes a VHDL-based simulation study we have conducted to investigate the RISC core design issues for high-speed scalable ATM host-network interface. The simulation results have shown that the three-stage pipeline RISC core supported with forwarding mechanism and delayed branch technique can process all the ATM interface codes without performance penalty due to the read-after-write data hazards and conditional branch processing. The core should be supported, however, with a forwarding mechanism to eliminate the stalling of the pipeline due to the processing of the conditional branch instructions. Also, the core structure should include a content addressable memory and direct memory access and support a simple instruction set. Also, the results show that a cost-effective RISC core could support a wide range of ATM user-network speeds.