Performance driven analog layout compiler

An approach to developing an automated analog layout compiler which results in a circuit layout based on a user-specified performance is described. The final layout is derived from sensitivities of the circuit performance with respect to layout interconnect parasitics and recognition rules of various configurations and topologies. The parasitic effects, which are important from an analog layout point of view, are minimized by this approach. This methodology is currently implemented in an analog circuit layout compiler.<<ETX>>

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