Stochastic Mixed-Signal VLSI Architecture for High-Dimensional Kernel Machines

A mixed-signal paradigm is presented for high-resolution parallel inner-product computation in very high dimensions, suitable for efficient implementation of kernels in image processing. At the core of the externally digital architecture is a high-density, low-power analog array performing binary-binary partial matrix-vector multiplication. Full digital resolution is maintained even with low-resolution analog-to-digital conversion, owing to random statistics in the analog summation of binary products. A random modulation scheme produces near-Bernoulli statistics even for highly correlated inputs. The approach is validated with real image data, and with experimental results from a CID/DRAM analog array prototype in 0.5 µm CMOS.

[1]  Allen Gersho,et al.  Vector quantization and signal compression , 1991, The Kluwer international series in engineering and computer science.

[2]  Alan H. Kramer Array-based analog computation , 1996, IEEE Micro.

[3]  G. Cauwenberghs,et al.  A Charge-Based CMOS Parallel Analog Vector Quantizer , 1994, NIPS 1994.

[4]  Gert Cauwenberghs,et al.  Charge-mode parallel architecture for matrix-vector multiplication , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[5]  Gert Cauwenberghs,et al.  Charge-mode parallel architecture for vector-matrix multiplication , 2001 .

[6]  Volnei A. Pedroni,et al.  Pattern matching and parallel processing with CCD technology , 1992, [Proceedings 1992] IJCNN International Joint Conference on Neural Networks.

[7]  Alan F. Murray,et al.  Synaptic Weight Noise During MLP Learning Enhances Fault-Tolerance, Generalization and Learning Trajectory , 1992, NIPS.

[8]  E. Sanchez-Sinencio,et al.  A general purpose neuro-image processor architecture , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[9]  Tomaso A. Poggio,et al.  A general framework for object detection , 1998, Sixth International Conference on Computer Vision (IEEE Cat. No.98CH36271).

[10]  Vladimir N. Vapnik,et al.  The Nature of Statistical Learning Theory , 2000, Statistics for Engineering and Information Science.

[11]  Amnon Yariv,et al.  A parallel analog CCD/CMOS neural network IC , 1991, IJCNN-91-Seattle International Joint Conference on Neural Networks.

[12]  A. Chiang,et al.  A programmable CCD signal processor , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[13]  M. J. Howes,et al.  Charge-coupled devices and systems , 1979 .

[14]  F. J. Kub,et al.  Programmable analog vector-matrix multipliers , 1990 .

[15]  Brian Kingsbury,et al.  SPERT-II: a vector microprocessor system and its application to large problems in backpropagation training , 1996, Proceedings of Fifth International Conference on Microelectronics for Neural Networks.

[16]  Gert Cauwenberghs,et al.  Learning on Silicon: Adaptive VLSI Neural Systems , 1999 .