An Exact Approach for GPC-Based Compressor Tree Synthesis

[1]  Yusuke Matsunaga,et al.  Multi-Operand Adder Synthesis Targeting FPGAs , 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[2]  Yusuke Matsunaga,et al.  Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[3]  Paolo Ienne,et al.  Exploiting fast carry-chains of FPGAs for designing compressor trees , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[4]  Paolo Ienne,et al.  Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming , 2008, 2008 Design, Automation and Test in Europe.

[5]  Paolo Ienne,et al.  Efficient synthesis of compressor trees on FPGAs , 2008, 2008 Asia and South Pacific Design Automation Conference.

[6]  Paolo Ienne,et al.  Automatic Synthesis of Compressor Trees: Reevaluating Large Counters , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[7]  R. Ravi,et al.  Optimal Circuits for Parallel Multipliers , 1998, IEEE Trans. Computers.

[8]  Vojin G. Oklobdzija,et al.  Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..