AN ACCURATE BRIDGING FAULT TEST PATTERN GENERATOR

Test pattern generation for bridging faults has been considered impractical. This paper presents an accurate bridging fault test pattern generator Lhat requires only a gate-level implementation of the circuit. No transistorlevel simulations are required during test pattern generation. Results presented for the ISCAS'85 benchmark circuits indicate that this test pattern generator is 8 practical solution to a problem that must be solved in order to detect the failures that occur in modern VLSI circuits.

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