Optimized Design Implementation of Direct Memory-Based Hardware for Efficient Resource- Constraint Digital Signal Processing Systems

An advance approach for Direct-Memory-Based hardware for area-delay-power efficient systems for commonly encountered computation-intensive cores of digital signal processing (DSP) systems is presented by combining three techniques, where the memory-size is reduced to one-eighth at the cost of some increase in combinational circuit complexity for signed magnitude numbers. Each of these techniques results in the reduction of the memory size by a factor of two. It is shown that by efficiently combining sign-bit exclusion technique, a different form of anti-symmetric product coding (APC) and a modified odd-multiple-storage (OMS) scheme, we get an optimized direct-memory-based multiplication hardware for resource-constraint DSP systems which provides a reduction in memory size to one-eighth over conventional direct-memorybased hardware, at the cost of a marginal area overhead. The proposed design for small input sizes can be used for efficient implementation of high-precision multiplication by input operand decomposition. The proposed optimized design also offers almost 87.5% and 85% reductions in directmemory size for L=5 bits and L=6 bits signed-magnitude numbers respectively, over conventional direct-memory size. Keywords— Digital signal processing (DSP), direct-memorybased computing, very large scale integration (VLSI).