Challenges and Solutions in Emerging Memory Testing

The research and prototyping of new memory technologies are getting a lot of attention in order to enable new (computer) architectures and provide new opportunities for today's and future applications. Delivering high quality and reliability products was and will remain a crucial step in the introduction of new technologies. Therefore, appropriate fault modelling, test development and design for testability (DfT) is needed. This paper overviews and discusses the challenges and the emerging solutions in testing three classes of memories: 3D stacked memories, Resistive memories and Spin-Transfer-Torque Magnetic memories. Defects mechanisms, fault models, and emerging test solutions will be discussed.

[1]  Janusz Nowak,et al.  Analytical MRAM test , 2014, 2014 International Test Conference.

[2]  T. Kuwata,et al.  Design and measurements of test element group wafer thinned to 10 /spl mu/m for 3D system in package , 2004, Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).

[3]  Narayanan Vijaykrishnan,et al.  Design Space Exploration for 3-D Cache , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Jagan Singh Meena,et al.  Overview of emerging nonvolatile memory technologies , 2014, Nanoscale Research Letters.

[5]  Bruce C. Kim,et al.  Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects , 2012, J. Electron. Test..

[6]  R. Waser,et al.  Nanoscale cation motion in TaO(x), HfO(x) and TiO(x) memristive systems. , 2016, Nature nanotechnology.

[7]  Weisheng Zhao,et al.  Read disturbance issue for nanoscale STT-MRAM , 2015, 2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA).

[8]  G. Smith,et al.  Yield considerations in the choice of 3D technology , 2007, 2007 International Symposium on Semiconductor Manufacturing.

[9]  R. Tummala,et al.  Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV) , 2009, 2009 59th Electronic Components and Technology Conference.

[10]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[11]  D.D. Antono,et al.  1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[12]  Shijian Luo,et al.  3D Integration-Present and Future , 2008, 2008 10th Electronics Packaging Technology Conference.

[13]  Sachhidh Kannan,et al.  Detection, diagnosis, and repair of faults in memristor-based memories , 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

[14]  Qiang Xu,et al.  Test architecture design and optimization for three-dimensional SoCs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[15]  R. Waser,et al.  Electrochemical and thermochemical memories , 2008, 2008 IEEE International Electron Devices Meeting.

[16]  Gabriel H. Loh,et al.  3D-Integrated SRAM Components for High-Performance Microprocessors , 2009, IEEE Transactions on Computers.

[17]  Yervant Zorian,et al.  Testing 3D chips containing through-silicon vias , 2009, 2009 International Test Conference.

[18]  Hsien-Hsin S. Lee,et al.  A scanisland based design enabling prebond testability in die-stacked microprocessors , 2007, 2007 IEEE International Test Conference.

[19]  S. R. Narasimhan,et al.  Modeling of Crosstalk in Through Silicon Vias , 2013, IEEE Transactions on Electromagnetic Compatibility.

[20]  Antonis Papanikolaou,et al.  Three Dimensional System Integration , 2011 .

[21]  Arnaud Virazel,et al.  A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Poh Choon Chew,et al.  Through Silicon Via (TSV) redundancy - a high reliability, networking product perspective , 2012, 2012 14th International Conference on Electronic Materials and Packaging (EMAP).

[23]  Sachhidh Kannan,et al.  Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  3D ICs with TSVs—Design Challenges and Requirements , 2012 .

[25]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[26]  Vivek Chickermane,et al.  DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks , 2012, 2012 IEEE International Test Conference.

[27]  Xiaoxia Wu,et al.  Test-access mechanism optimization for core-based three-dimensional SOCs , 2008, 2008 IEEE International Conference on Computer Design.

[28]  Said Hamdioui,et al.  Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories , 2011, 2011 Sixteenth IEEE European Test Symposium.

[29]  Heiko Ehrenberg,et al.  IEEE Std 1581 — A standardized test access methodology for memory devices , 2011, 2011 IEEE International Test Conference.

[30]  Tadahiro Kuroda,et al.  A 1Tb/s 3W Inductive-Coupling Transceiver Chip , 2007, 2007 Asia and South Pacific Design Automation Conference.

[31]  Seyed Nima Mozaffari,et al.  Fast march tests for defects in resistive memory , 2015, Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15).

[32]  Linggang Zhu,et al.  An overview of materials issues in resistive random access memory , 2015 .

[33]  Elena I. Vatajelu,et al.  Nonvolatile memories: Present and future challenges , 2014, 2014 9th International Design and Test Symposium (IDT).

[34]  D.P. Siewiorek,et al.  Testing of digital systems , 1981, Proceedings of the IEEE.

[35]  Qiang Xu,et al.  Yield enhancement for 3D-stacked memory by redundancy sharing across dies , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[36]  Ashok Sharma.  Advanced Semiconductor Memories: Architectures, Designs, and Applications , 2009 .

[37]  R. Waser,et al.  Resistive Switching: From Fundamentals of Nanoionic Redox Processes to Memristive Device Applications , 2016 .

[38]  Mottaqiallah Taouil.  Yield and Cost Analysis or 3D Stacked ICs , 2014 .

[39]  T. Prodromakis,et al.  Spatially resolved TiOx phases in switched RRAM devices using soft X-ray spectromicroscopy , 2016, Scientific Reports.

[40]  Erik Jan Marinissen,et al.  Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[41]  Yu-Jen Huang,et al.  Post-bond test techniques for TSVs with crosstalk faults in 3D ICs , 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

[42]  Kaushik Roy,et al.  Spin-Transfer Torque Memories: Devices, Circuits, and Systems , 2016, Proceedings of the IEEE.

[43]  Jin-Fu Li,et al.  Fault modeling and testing of 1T1R memristor memories , 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

[44]  J. Katine,et al.  Device implications of spin-transfer torques , 2008 .

[45]  Sorin Cotofana,et al.  Is TSV-based 3D integration suitable for inter-die memory repair? , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[46]  Mehdi Baradaran Tahoori,et al.  Read disturb fault detection in STT-MRAM , 2014, 2014 International Test Conference.

[47]  Hsien-Hsin S. Lee,et al.  Test Challenges for 3D Integrated Circuits , 2009, IEEE Design & Test of Computers.

[48]  E. Pérez,et al.  Geometric conductive filament confinement by nanotips for resistive switching of HfO2-RRAM devices with high performance , 2016, Scientific Reports.

[49]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[50]  Bernard Dieny,et al.  Introduction to Magnetic Random-Access Memory , 2016 .

[51]  Elena I. Vatajelu,et al.  On the impact of process variability and aging on the reliability of emerging memories (Embedded tutorial) , 2014, 2014 19th IEEE European Test Symposium (ETS).

[52]  Fangming Ye,et al.  TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation , 2012, DAC Design Automation Conference 2012.

[53]  Young-Hyun Jun,et al.  8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.

[54]  Jean Michel Portal,et al.  Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections , 2009, 2009 14th IEEE European Test Symposium.

[55]  Cheng-Wen Wu,et al.  Write Disturbance Modeling and Testing for MRAM , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[56]  Vladimir Pasca,et al.  Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis , 2011, 2011 12th Latin American Test Workshop (LATW).

[57]  Taewhan Kim,et al.  Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew , 2010, International Conference on Green Computing.

[58]  R. Dean Adams,et al.  High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test , 2002 .

[59]  Chong-Min Kyung,et al.  Cost-effective TSV redundancy configuration , 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

[60]  Erik Jan Marinissen,et al.  Interconnect test for 3D stacked memory-on-logic , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[61]  K. Soejima,et al.  A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer , 2006, 2006 International Electron Devices Meeting.

[62]  Fabrizio Lombardi,et al.  New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[63]  Xiaoxia Wu,et al.  Test-access mechanism optimization for core-based three-dimensional SOCs , 2010, Microelectron. J..

[64]  Xiaoxia Wu,et al.  Scan chain design for three-dimensional integrated circuits (3D ICs) , 2007, 2007 25th International Conference on Computer Design.

[65]  M. Julliere.  Tunneling between ferromagnetic films , 1975 .

[66]  TingTing Hwang,et al.  TSV Redundancy: Architecture and Design Issues in 3-D IC , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[67]  Jogender Singh,et al.  An Overview : Electron Beam-Physical Vapor Deposition Technology-Present and Future Applications , 1999 .

[68]  Qiang Xu,et al.  Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[69]  D. Stewart,et al.  The missing memristor found , 2008, Nature.

[70]  Xi Liu,et al.  Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[71]  Arnaud Virazel,et al.  Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains , 2013, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS).

[72]  Kaushik Roy,et al.  AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[73]  Said Hamdioui,et al.  On Defect Oriented Testing for Hybrid CMOS/Memristor Memory , 2011, 2011 Asian Test Symposium.

[74]  Xu Qian,et al.  Excellent resistive switching properties of atomic layer-deposited Al2O3/HfO2/Al2O3 trilayer structures for non-volatile memory applications , 2015, Nanoscale Research Letters.

[75]  N. Iguchi,et al.  A fast and low-voltage Cu complementary-atom-switch 1Mb array with high-temperature retention , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[76]  Vivek Chickermane,et al.  At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic , 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

[77]  Erik Jan Marinissen,et al.  Evaluation of TSV and micro-bump probing for wide I/O testing , 2011, 2011 IEEE International Test Conference.

[78]  P. Franzon,et al.  Buried bump and AC coupled interconnection technology , 2004, IEEE Transactions on Advanced Packaging.

[79]  Hung-Yin Tsai,et al.  Thermal stress analysis and failure mechanisms for through silicon via array , 2011, 13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.

[80]  Said Hamdioui,et al.  Testing Open Defects in Memristor-Based Memories , 2015, IEEE Transactions on Computers.

[81]  J. Wilson,et al.  AC coupled interconnect for dense 3-D ICs , 2003, 2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515).

[82]  Byung-Gook Park,et al.  Accurate analysis of conduction and resistive-switching mechanisms in double-layered resistive-switching memory devices , 2012 .

[83]  Krishnendu Chakrabarty,et al.  Test-Cost Modeling and Optimal Test-Flow Selection of 3-D-Stacked ICs , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[84]  R. W. Dave,et al.  A 4-Mb toggle MRAM based on a novel bit and switching method , 2005, IEEE Transactions on Magnetics.

[85]  Gabriel H. Loh,et al.  3D-Stacked Memory Architectures for Multi-core Processors , 2008, 2008 International Symposium on Computer Architecture.

[86]  C. Jahnes,et al.  2.5D and 3D technology challenges and test vehicle demonstrations , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[87]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[88]  Alex Ramírez,et al.  On the memory system requirements of future scientific applications: Four case-studies , 2011, 2011 IEEE International Symposium on Workload Characterization (IISWC).

[89]  Fangming Ye,et al.  TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[90]  Erik Jan Marinissen,et al.  Quality versus cost analysis for 3D Stacked ICs , 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

[91]  Jacques-Olivier Klein,et al.  Design of TAS-MRAM prototype for NV embedded memory applications , 2010, 2010 IEEE International Memory Workshop.

[92]  Shimeng Yu,et al.  Overview of resistive switching memory (RRAM) switching mechanism and device modeling , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[93]  Frederick T. Chen,et al.  RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme , 2015, IEEE Transactions on Computers.

[94]  Krishnendu Chakrabarty,et al.  TSV Stress-Aware ATPG for 3D Stacked ICs , 2012, 2012 IEEE 21st Asian Test Symposium.

[95]  Yervant Zorian,et al.  Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[96]  Sachhidh Kannan,et al.  Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories , 2013, IEEE Transactions on Nanotechnology.

[97]  R. Waser,et al.  Thermochemical resistive switching: materials, mechanisms, and scaling projections , 2011 .

[98]  P. Reed,et al.  Design aspects of a microprocessor data cache using 3D die interconnect technology , 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

[99]  Joungho Kim,et al.  Disconnection failure model and analysis of TSV-based 3D ICs , 2012, 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS).

[100]  Tong Zhang,et al.  Architecture design exploration of three-dimensional (3D) integrated DRAM , 2009, 2009 10th International Symposium on Quality Electronic Design.

[101]  Said Hamdioui,et al.  DfT schemes for resistive open defects in RRAMs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[102]  Arijit Raychowdhury,et al.  Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays , 2016, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[103]  Lirida Alves de Barros Naviner,et al.  Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy , 2016, Materials.

[104]  Xiaoxiong Gu,et al.  Analysis of TSV geometric parameter impact on switching noise in 3D power distribution network , 2014, 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).

[105]  Erik Jan Marinissen,et al.  Testing TSV-based three-dimensional stacked ICs , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[106]  Ee Wah Lim,et al.  Conduction Mechanism of Valence Change Resistive Switching Memory: A Survey , 2015 .

[107]  Cheng-Wen Wu,et al.  MRAM defect analysis and fault modeling , 2004, 2004 International Conferce on Test.

[108]  Tao Zhang,et al.  A customized design of DRAM controller for on-chip 3D DRAM stacking , 2010, IEEE Custom Integrated Circuits Conference 2010.

[109]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.