A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA

This paper presents a low-complexity, high-speed VLSI decoder architecture and its FPGA implementation for Euclidian geometry (EG) based quasi-cyclic (QC) low-density parity-check (LDPC) codes. In the design, various optimizations are employed to increase the clock speed. More parallelism is enabled for the partially parallel decoding architecture through the introduction of small hardware overhead. An efficient non-uniform quantization scheme is proposed to reduce the size of soft message memories without sacrificing the decoding performance. Synthesis results show that the proposed decoder for a (8176, 7156) EG-LDPC code can achieve a maximum (information) decoding throughput over 170 Mbps on Xilinx Virtex II FPGA when performing 15 iterations

[1]  Daniel J. Costello,et al.  LDPC block and convolutional codes based on circulant matrices , 2004, IEEE Transactions on Information Theory.

[2]  Yanni Chen,et al.  A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder , 2003, GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489).

[3]  Zhongfeng Wang,et al.  Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[4]  Jinghu Chen,et al.  Near optimum universal belief propagation based decoding of low-density parity check codes , 2002, IEEE Trans. Commun..

[5]  Shu Lin,et al.  Near-Shannon-limit quasi-cyclic low-density parity-check codes , 2003, IEEE Transactions on Communications.

[6]  Marc P. C. Fossorier,et al.  Quasi-Cyclic Low-Density Parity-Check Codes From Circulant Permutation Matrices , 2004, IEEE Trans. Inf. Theory.

[7]  Zongwang Li,et al.  Efficient encoding of quasi-cyclic low-density parity-check codes , 2006, IEEE Trans. Commun..

[8]  Zongwang Li,et al.  A class of good quasi-cyclic low-density parity check codes based on progressive edge growth graph , 2004, Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004..

[9]  Shu Lin,et al.  Near-Shannon-limit quasi-cyclic low-density parity-check codes , 2004, IEEE Trans. Commun..

[10]  Joseph R. Cavallaro,et al.  Semi-parallel reconfigurable architectures for real-time LDPC decoding , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

[11]  Keshab K. Parhi,et al.  Area efficient decoding of quasi-cyclic low density parity check codes , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[12]  Keshab K. Parhi,et al.  A 54 Mbps (3,6)-regular FPGA LDPC decoder , 2002, IEEE Workshop on Signal Processing Systems.

[13]  Rüdiger L. Urbanke,et al.  Efficient encoding of low-density parity-check codes , 2001, IEEE Trans. Inf. Theory.

[14]  Wayne Luk,et al.  A flexible hardware encoder for low-density parity-check codes , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[15]  Tong Zhang,et al.  On finite precision implementation of low density parity check codes decoder , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).