AES encryption engines of many core processor arrays on FPGA by using parallel, pipeline and sequential technique

Now a days, the number of Internet and wireless communications users has rapidly grown and that increases demand for security measures to protect user data transmitted over openchannels. Cryptographic algorithms are very essential for security of the systems worldwide. In December 2001, the National Institute of Standards and Technology (NIST) of the United States selected the Rijndael algorithm as the suitable Advanced Encryption Standard (AES) to replace the Data Encryption Standard (DES) algorithm. AES can be considered the most widely used modern symmetric key encryption standard. The AES algorithm is a block cipher that can encrypt and decrypt digital information. This paper explores task level parallelism with three concurrently working AES modules to achieve less area and high throughput. With the area optimization techniques, the system becomes area and time efficient as the throughput of 5.751Gbps is achieved with less area. The design is implemented in Zynq(xc7z020-2clg484) device and tested on Zedboard. As three different implementations of AES are explored, the design has three times higher throughput with less area than the other systems. To encrypt/decrypt a file using the AES algorithm, the file must undergo a set of complex computational steps. Therefore a software implementation of AES algorithm would be slow and consume large amount of time to complete. The immense increase of both stored and transferred data in the recent years had made this problem even more serious when the need to encrypt/decrypt such data arises.