Developing a gate-array capability at a research and development laboratory

This paper describes our experiences in developing a gate-array capability for low-volume applications in a research and development (R and D) laboratory. By purchasing unfinished wafers and doing the customization steps in-house, we have been able to shorten turnaround time to as little as one week and to reduce the direct costs to as low as $5K per design. At our Laboratory, we have several hundred design engineers supporting a variety of research programs. Designs generally require fast turnaround (a few weeks to a few months) and very low volumes (1 to 25). Design costs must be kept at a minimum. After reviewing available commercial gate-array design and fabrication services, we have determined our objectives would best be met by using our existing internal integrated-circuit fabrication facilities, our present COMPUTERVISION interactive graphics layout system, and our extensive computational capabilities. We discuss the reasons and the approach we have taken at LLNL in; selecting a particular gate-array wafer, adapting a particular logic simulation program, and how we have enhanced layout aids. We will also describe how we are doing testing of the customized chips. An important part of our project is how we are introducing the technology to internal designers through more » the development of a course. The content, schedule, and results of our internal gate-array course recently completed are discussed. Finally, our current problem areas and our near-term plans are presented. « less