A VLSI implementation of a reconfigurable rational filter

We propose an implementation of a reconfigurable system which exploits the features and the robustness of rational filters in order to accomplish various image processing tasks. This particular architecture is able to implement various different algorithms as noise-smoothing edge preserving filtering, interpolation, blocking artifacts removal. The architecture is structured as a bit-level pipeline and can work at frequency of 200 MHz, maintaining a quite small size of 7/spl times/5 mm/sup 2/.

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