A review of multiple-valued memory technology

This paper provides a brief overview of semiconductor memory design from the perspective of the impact multiple-valued circuit techniques are making on modern day implementations. The focus is primarily on CMOS-related technologies.

[1]  Takahiro Hanyu,et al.  Functionally separated, multiple-valued content-addressable memory and its applications , 1995 .

[2]  Y. Nakagome,et al.  A 16-levels/cell dynamic memory , 1985 .

[3]  Kenneth J. Schultz Content-addressable memory core cells A survey , 1997, Integr..

[4]  J. F. Verwey,et al.  Nonvolatile Semiconductor Memories , 1976 .

[5]  P. Glenn Gulak,et al.  Architectures for large-capacity CAMs , 1995, Integr..

[6]  C. G. Sodini,et al.  A ternary content addressable search engine , 1989 .

[7]  E.K.F. Lee,et al.  Error correction technique for multivalued MOS memory , 1991 .

[8]  David A. Rich,et al.  A Survey of Multivalued Memories , 1986, IEEE Transactions on Computers.

[9]  Greg Atwood,et al.  A multilevel-cell 32 Mb flash memory , 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).

[10]  中島 謙,et al.  A 4-level Storage 4Gb DRAM , 1997 .

[11]  P. Glenn Gulak,et al.  A multiple-valued ferroelectric content-addressable memory , 1996, Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96).

[12]  T. Hanyu,et al.  Design of a one-transistor-cell multiple-valued CAM , 1996, IEEE Journal of Solid-State Circuits.

[13]  M. Fukuma,et al.  A 60 ns 1 Mb nonvolatile ferroelectric memory with non-driven cell plate line write/read scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[14]  A. Sheikholeslami,et al.  Transient modeling of ferroelectric capacitors for nonvolatile memories , 1996, IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control.

[15]  S. Tanaka,et al.  A new flash E2PROM cell using triple polysilicon technology , 1984, 1984 International Electron Devices Meeting.

[16]  Michel Declercq,et al.  Implementation of a learning Kohonen neuron based on a new multilevel storage technique , 1991 .

[17]  Toshiro Itani,et al.  A 1-Gb DRAM for file applications , 1995 .

[18]  T. Matano,et al.  A 4-level storage 4 Gb DRAM , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.