Detecting context sensitive hot spots in standard cell libraries

Advances in lithography patterning have been the primary driving force in microelectronics manufacturing processes. With the increasing gap between the wavelength of the optical source and feature sizes, the accompanying strong diffraction effects have a significant impact on the pattern fidelity of on-silicon layout shapes. Layout patterns become highly sensitive to those context shapes lying within the optical radius of influence. Under such optical proximity effects, manufacturability hot spots such as necking and bridging may occur. Studies have shown that manufacturability hot spots are pattern dependent in nature and should be considered at the design stage [1]. It is desirable to detect these hot spots as early as possible in the design flow to minimize the costs for correction. In this work, we propose a hot spot prediction method based on a support vector machine technique. Given the location of a hot spot candidate and its context patterns, the proposed method is capable of efficiently predicting whether a candidate would become a hot spot. It takes just seconds to classify thousands of samples. Due to its computational efficiency, it is possible to use this method in physical design tools to rapidly assess the quality of printed patterns. We demonstrate one such application in which we evaluate the layout quality in the boundary region of standard cells. In the conventional standard cell layout optimization process, lithography simulation is the main layout verification method. Since it is a very time-consuming process, the iterative optimization approach between simulation and layout correction [2] takes a long time and only a limited number of context patterns can be explored. We show that with the proposed hot spot prediction method, for each standard cell, a much greater context pattern space can be explored, and the context sensitivity of a hot spot candidate located near a cell boundary can be estimated.