Design of synchronous decimal counter using reversible Toffoli–Fredkin Netlist

Investigations in reversible computation have been one of the notable dimensions among the emerging research domains. Reversible circuits promise near-zero heat dissipation resulting in a considerable amount of literary proposals. This article proposes a reversible synchronous decimal counter using Toffoli and Fredkin gates. Decimal counter forms an important Boolean specification as they are used for clock generators, frequency dividers, clock division, integrated oscillation, etc. Although literature witnesses exhaustive research in reversible mod-2/4/8/16 counters, there is a void in the domain of reversible decimal counters. We propose three designs D1, D2, and D3. Design D1 and D2 are synchronous decimal up and down counters, respectively, using Toffoli Netlist. Design D3 is the integration of designs D1 and D2 using the Fredkin Gate array. The proposed designs have been checked using a state-of-the-art optimization algorithm in literature and the results reflect our design to be best optimized. Peer analysis reflects a summary of existing literary proposals exhibiting the uniqueness of the proposed designs.