Composition and Verification of Condition/Event Systems

We consider different ways of combining discrete and timed condition/event systems in a modular, compositional way. In addition to the interconnection operators for discrete condition/event systems found in the literature, we introduce a new, powerful operator, called parallel interconnection operator. We introduce condition/event systems (CESs) as a model for continuoustime discrete event systems which communicate by exchanging two kinds of symbols, called condition and event symbols. Condition symbols are used to describe system states and can enable or disable state changes, whereas event symbols denote instantaneous actions and are used to trigger state changes. A special class of CESs are discrete condition/event systems (DCESs), which use a finite transition system to control the input/output behavior of the system. CESs and DCESs can be represented as block diagrams using signal flows for the connection between the system. These models are widely used in system engineering and control theory. We investigate the operators for connecting DCESs given in the literature, namely the cascade interconnection and the feedback connection operators. These operators are very restrictive in the way systems can be connected, and therefore, their usage is complicated and not very intuitive. We introduce the loop interconnection operator, which covers any connection between two systems, but this operator does not reach maximal flexibility for connections among more than two systems. Thus, we define the parallel interconnection operator, which allows arbitrary connections among a set of DCESs. This operator allows easy and intuitive handling of interconnected systems and does not have the strong restrictions of the previously defined operators. Quantitative timing, an important feature DCESs are not capable of, is added by introducing timed condition/event systems (TCESs), which are DCESs augmented with timers. We extend our parallel interconnection operator to TCESs, completing our goal of defining a flexible operator for composing DCESs and TCESs connected in an arbitrary way. An extensive example shows various possibilities how to verify properties of a system consisting of some interconnected TCESs. Obviously, compositional techniques are most promising for an efficient verification. We conclude this work by showing how a set of interconnected DCESs can be transformed into the input language of the model checking tool SMV. This offers another possibility to apply formal verification to condition/event systems.