Voltage deviate-domino circuits for low power high-speed applications using prescient innovation model

Abstract There are two main challenges in designing CMOS-based VLSI circuits in deep sub-micron technology due to leakage power and propagation delay. In this work proposed an advanced technique to design voltage deviate domino logic circuit for reduce the leakage power and reduce the propagation delay. But integrated circuits, a dominant part gradually consuming the clocking power, so this research work is mainly focused on the Design of Voltage Deviate-Domino Circuit (VDDC) and improve the performance of delay, Figure of Merit and power consumption using Prescient Innovation Model (PIM) technique. The proposed PIM voltage deviate domino logic is designed using spice model EDA tool with 0.18 µm ASIC technology. In voltage deviate domino circuit, the voltage variation in pull down the network is reduced to reduce the power usage of wide fan in (WFI) OR gates. The performance of proposed voltage deviate domino circuit is validated through simulation. The simulation results demonstrate the reduction improvement in the noise immunity, power consumption, delay and similar noise of results has to be demonstrate power reduction and speed change in voltage variation-Domino Circuit Registry file associated with the regular Registry file. During the evaluation phase, internal node inputs, clock and output are all lower, so the proposed PIM domino logic circuits is initially precharged high, while demonstrating that there is a higher choice in lower power noise applications.