On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG

Arithmetic-function modules, which are available in many circuits, can be utilized to generate test patterns and compact test responses. An accumulator-based scheme along with a procedure to find maximum-length nonlinear sequences for bit-serial test-pattern generators is proposed. The proposed scheme achieves good fault coverage with low hardware overhead and short test sequences

[1]  Albrecht P. Stroele Bit serial pattern generation and response compaction using arithmetic functions , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[2]  Janusz Rajski,et al.  Multiplicative window generators of pseudo-random test vectors , 1996, Proceedings ED&TC European Design and Test Conference.

[3]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[4]  Albrecht P. Stroele,et al.  BIST Pattern Generators Using Addition and Subtraction Operations , 1997, J. Electron. Test..

[5]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[6]  Hans-Joachim Wunderlich,et al.  BIST for systems-on-a-chip , 1998, Integr..

[7]  Mark E. Law,et al.  Two-dimensional semiconductor device simulation of trap-assisted generation-recombination noise under periodic large-signal conditions and its use for developing cyclostationary circuit simulation models , 2003 .

[8]  Paolo Prinetto,et al.  On applying the set covering model to reseeding , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[9]  Giorgos Dimitrakopoulos,et al.  Bit-serial test pattern generation by an accumulator behaving as a non-linear feedback shift register , 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

[10]  Haridimos T. Vergos,et al.  On accumulator-based bit-serial test response compaction schemes , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

[11]  Ioannis Voyiatzis,et al.  Test vector embedding into accumulator-generated sequences: a linear-time solution , 2005, IEEE Transactions on Computers.

[12]  Janusz Rajski,et al.  Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns , 1996, IEEE Trans. Computers.

[13]  Dimitris Nikolos,et al.  Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[14]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[15]  Kartikeya Mayaram,et al.  Algorithms for transient three-dimensional mixed-level circuit and device simulation , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Donald E. Knuth,et al.  The art of computer programming. Vol.2: Seminumerical algorithms , 1981 .

[17]  Albrecht P. Stroele Test response compaction using arithmetic functions , 1996, Proceedings of 14th VLSI Test Symposium.

[18]  Janusz Rajski,et al.  Test responses compaction in accumulators with rotate carry adders , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[20]  Janusz Rajski,et al.  Arithmetic Built-In Self-Test for Embedded Systems , 1997 .

[21]  Salvador Manich,et al.  On the selection of efficient arithmetic additive test pattern generators [logic test] , 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

[22]  Emmanouil Kalligeros,et al.  On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST , 2002, J. Electron. Test..

[23]  David Thomas,et al.  The Art in Computer Programming , 2001 .