Built-in self-diagnosis and test time reduction techniques for NAND flash memories
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[1] Kewal K. Saluja,et al. Fault Models and Test Procedures for Flash Memory Disturbances , 2001, J. Electron. Test..
[2] Kewal K. Saluja,et al. Optimizing program disturb fault tests using defect-based testing , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3] Jin-Fu Li,et al. A built-in self-test and self-diagnosis scheme for embedded SRAM , 2000, Proceedings of the Ninth Asian Test Symposium.
[4] Jen-Chieh Yeh,et al. Flash memory built-in self-test using March-like algorithms , 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.
[5] Kewal K. Saluja,et al. Simulating program disturb faults in flash memories using SPICE compatible electrical model , 2003 .
[6] Jen-Chieh Yeh,et al. Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[7] Jen-Chieh Yeh,et al. Diagonal test and diagnostic schemes for flash memories , 2002, Proceedings. International Test Conference.
[8] Kewal K. Saluja,et al. Flash memory disturbances: modeling and test , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.
[9] Jin-Fu Li,et al. A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM , 2002, J. Electron. Test..