March tests for realistic faults in two-port memories

This paper starts with an overview of realistic faults models for two-port memories, divided into single-port faults and unique two-port faults. The latter faults can not be detected with the conventional single-port memory tests; they require special tests. Thereafter the paper presents a set of four march tests detecting the unique two-port faults. Three of the tests have a time complexity of /spl theta/(n) and one of /spl theta/ (/spl radic/n), whereby n is the size of the two-port memory cell array. Two of the four tests have been implemented at Intel and applied to 1500 two-port memories passing all single port tests. The test results show that two dies fail to pass the implemented tests, which means that the tests are superior.

[1]  Said Hamdioui,et al.  Port interference faults in two-port memories , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[2]  Sanjay Gupta,et al.  Built-in self-test for multi-port RAMs , 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

[3]  B. Nadeau-Dostie,et al.  A 5 Gb/s 9-port application specific SRAM with built-in self test , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.

[4]  Bernard Courtois,et al.  Built-in self-test in multi-port RAMs , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[5]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[6]  Benoit Nadeau-Dostie,et al.  Serial interfacing for embedded-memory testing , 1990, IEEE Design & Test of Computers.

[7]  Manuel J. Raposa.  Dual port static RAM testing , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[8]  Michael Nicolaidis,et al.  Testing complex couplings in multiport memories , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Said Hamdioui,et al.  Consequences of port restrictions on testing two-port memories , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[10]  T. Matsumura.  An efficient test method for embedded multi-port RAM with BIST circuitry , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.

[11]  Said Hamdioui,et al.  Fault models and tests for two-port memories , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).