Systematic defect identification through layout snippet clustering

Systematic defects due to design-process interactions are a dominant component of integrated circuit (IC) yield loss in nano-scaled technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that affect the product. This paper describes a method that uses diagnosis to identify layout features that do not yield as expected. Specifically, clustering techniques are applied to layout snippets of diagnosis-implicated regions from (ideally) a statistically-significant number of IC failures for identifying feature commonalties. Experiments involving an industrial chip demonstrate the identification of possible systematic yield loss due to lithographic hotspots.

[1]  Leendert M. Huisman,et al.  Data mining integrated circuit fails with fail commonalities , 2004, 2004 International Conferce on Test.

[2]  Sandeep Kumar Goel,et al.  Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study , 2009, 2009 27th IEEE VLSI Test Symposium.

[3]  Tracy Larrabee,et al.  Multiplets, models, and the search for meaning: improving per-test fault diagnosis , 2002, Proceedings. International Test Conference.

[4]  Camelia Hora,et al.  Systematic defects in deep sub-micron technologies , 2004, 2004 International Conferce on Test.

[5]  Yoan Miche,et al.  Mixture Models and EM , 2007 .

[6]  Janusz Rajski,et al.  Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement , 2007, 12th IEEE European Test Symposium (ETS'07).

[7]  Jitendra Malik,et al.  Normalized cuts and image segmentation , 1997, Proceedings of IEEE Computer Society Conference on Computer Vision and Pattern Recognition.

[8]  Costas J. Spanos,et al.  Automatic hotspot classification using pattern-based clustering , 2008, SPIE Advanced Lithography.

[9]  J. MacQueen.  Some methods for classification and analysis of multivariate observations , 1967 .

[10]  Resve A. Saleh,et al.  Exact evaluation of diagnostic test resolution , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[11]  Srikanth Venkataraman,et al.  POIROT: a logic fault diagnosis tool and its applications , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[12]  Meena Mahajan,et al.  The Planar k-means Problem is NP-hard I , 2009 .

[13]  Wojciech Maly,et al.  Evaluating yield and testing impact of sub-wavelength lithography , 2010, 2010 28th VLSI Test Symposium (VTS).

[14]  Franz Aurenhammer,et al.  A Novel Type of Skeleton for Polygons , 1996 .

[15]  P. Mahalanobis.  On the generalized distance in statistics , 1936 .

[16]  Wu-Tung Cheng,et al.  Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data , 2008, 2008 IEEE International Test Conference.

[17]  Costas J. Spanos,et al.  Clustering and pattern matching for an automatic hotspot classification and detection system , 2009, Advanced Lithography.

[18]  Anil K. Jain,et al.  Data clustering: a review , 1999, CSUR.

[19]  Jie Yang,et al.  DRC Plus: augmenting standard DRC with pattern matching on 2D geometries , 2007, SPIE Advanced Lithography.

[20]  R. D. Blanton,et al.  Precise failure localization using automated layout analysis of diagnosis candidates , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[21]  B. Koenemann.  Design/process learning from electrical test , 2004, ICCAD 2004.

[22]  Yen-Tzu Lin,et al.  Controlling DPPM through Volume Diagnosis , 2009, 2009 27th IEEE VLSI Test Symposium.

[23]  C. Huang,et al.  Using design based binning to improve defect excursion control for 45nm production , 2007, 2007 International Symposium on Semiconductor Manufacturing.

[24]  Wojciech Maly,et al.  Yield estimation model for VLSI artwork evaluation , 1983 .

[25]  Nasser M. Nasrabadi,et al.  Pattern Recognition and Machine Learning , 2006, Technometrics.

[26]  R. D. Blanton,et al.  Automated failure population creation for validating integrated circuit diagnosis methods , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[27]  Irith Pomeranz,et al.  On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[28]  Leendert M. Huisman,et al.  Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[29]  S. Jansen,et al.  Utilizing Design Layout Information to Improve Efficiency of SEM Defect Review Sampling , 2008, 2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.

[30]  Michael I. Jordan,et al.  On Spectral Clustering: Analysis and an algorithm , 2001, NIPS.

[31]  Masahiro Takakura,et al.  A persistent diagnostic technique for unstable defects , 2002, Proceedings. International Test Conference.

[32]  David Abercrombie,et al.  Value-added defect testing techniques , 2005, IEEE Design & Test of Computers.

[33]  Tejas Jhaveri,et al.  Enabling technology scaling with "in production" lithography processes , 2008, SPIE Advanced Lithography.

[34]  Jitendra Malik,et al.  Normalized Cuts and Image Segmentation , 2000, IEEE Trans. Pattern Anal. Mach. Intell..

[35]  Wu-Tung Cheng,et al.  Yield Learning with Layout-aware Advanced Scan Diagnosis , 2006 .

[36]  Inderjit S. Dhillon,et al.  Concept Decompositions for Large Sparse Text Data Using Clustering , 2004, Machine Learning.

[37]  Luciano da Fontoura Costa,et al.  2D Euclidean distance transform algorithms: A comparative survey , 2008, CSUR.

[38]  Janusz Rajski,et al.  A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis , 2006, 2006 IEEE International Test Conference.

[39]  S.D. Millman,et al.  Diagnosing CMOS bridging faults with stuck-at fault dictionaries , 1990, Proceedings. International Test Conference 1990.

[40]  R. D. Blanton,et al.  A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior , 2006, 2006 IEEE International Test Conference.