JTAG-based vector and chain management for system test
暂无分享,去创建一个
We present an embedded boundary-scan test vector management solution that ensures the correct version of test vectors is applied to the unit under test (UUT). This new vector management approach leverages the system-level boundary-scan multi-drop architecture employed in some high availability electronic systems. Compared to previous methods that do not use system-level boundary-scan resources for vector management, this new approach ensures that the correct boundary-scan vectors are retrieved from the UUT without affecting its operation and requires minimal UUT functionality to execute. The performance and effectiveness of this technique is shown using an actual design example that has been realized in a new product
[1] Mike Ricchetti,et al. Infrastructure IP for configuration and test of boards and systems , 2003, IEEE Design & Test of Computers.
[2] Mike Ricchetti,et al. An Embedded Test and Configuration Processor for Self-Testable and Field Re-Configurable Systems , 2003 .
[3] Bradford G. Van Treuren,et al. Embedded boundary scan , 2003, IEEE Design & Test of Computers.