On-Chip ESD detection circuit for system-level ESD protection design

A new on-chip CR-based electrostatic discharge (ESD) detection circuit for system-level ESD protection design is proposed in this work. The circuit performance to detect positive or negative electrical transients generated by system-level ESD tests has been analyzed in HSPICE simulation and verified in silicon chip. The experimental results in a 0.13-µm CMOS process have confirmed that the proposed detection circuit can detect ESD-induced transient disturbance during system-level ESD zapping. The detection results can be used as system recovery firmware index to improve the immunity of CMOS IC products against system-level ESD stress.