Tailoring Tests for Functional Binning of Integrated Circuits

In recent years, a number of high level applications have been reported to be tolerant to errors resulting from a sizable fraction of all single stuck-at faults in hardware. Production testing of devices targeted towards such applications calls for a test vector set that is tailored to maximize the coverage of faults that lead to functionally malignant errors while minimizing the coverage of faults that produce functionally benign errors. Given a partitioning of the fault set as benign and malignant, and a complete test vector set that covers all faults, in this paper, we formulate an integer linear programming (ILP) problem to find an optimal test vector set that ensures 100% coverage of malignant faults and minimizes coverage of benign faults.We also propose a test strategy based on selectively masking appropriate outputs of the circuit to partition the circuits at production test into three bins - malignant, benign, and fault-free. As a case study, we demonstrate the proposed ILP based test optimization and functional binning on three adder circuits: 16-bit ripple carry adder, 16-bit carry lookahead adder, and 16-bit carry select adder. We find that the proposed ILP based optimization gives a reduction of about 90% in fault coverage of benign faults while ensuring 100% coverage of malignant faults. This typically translates to an (early manufacturing) yield improvement of over 20% over what would have been the yield if both malignant and benign faults are targeted without distinction by the test vectorset.

[1]  Melvin A. Breuer,et al.  Defect and error tolerance in the presence of massive numbers of defects , 2004, IEEE Design & Test of Computers.

[2]  Melvin A. Breuer,et al.  A novel test methodology based on error-rate to support error-tolerance , 2005, IEEE International Conference on Test, 2005..

[3]  Sandeep K. Gupta,et al.  Threshold Testing: Improving Yield for Nanoscale VLSI , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Shekhar Y. Borkar,et al.  Design perspectives on 22nm CMOS and beyond , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[5]  Yuki Yoshikawa,et al.  A Practical Approach to Threshold Test Generation for Error Tolerant Circuits , 2009, 2009 Asian Test Symposium.

[6]  Melvin A. Breuer,et al.  An Illustrated Methodology for Analysis of Error Tolerance , 2008, IEEE Design & Test of Computers.

[7]  Melvin A. Breuer,et al.  Estimating Error Rate in Defective Logic Using Signature Analysis , 2007, IEEE Transactions on Computers.

[8]  Yuki Yoshikawa,et al.  A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic , 2010, 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications.

[9]  Melvin A. Breuer,et al.  An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Chun-Hsien Chou,et al.  A perceptually tuned subband image coder based on the measure of just-noticeable-distortion profile , 1994, Proceedings of 1994 IEEE International Symposium on Information Theory.

[11]  Melvin A. Breuer,et al.  Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Robert H. Dennard,et al.  CMOS scaling for high performance and low power-the next ten years , 1995, Proc. IEEE.

[13]  Sandeep K. Gupta,et al.  ERTG: A test generator for error-rate testing , 2007, 2007 IEEE International Test Conference.