State space techniques have proven to be useful for measuring and improving the coverage of test vectors that are used during functional validation via simulation. By comparing the state and edge coverage provided by tests with that which is possible in the design's state graph, the designer can estimate how well tested the design is and identify areas that need better testing. Unfortunately, for many interesting designs, the full state graph may be too large to fully explore, or if it is explorable, the resulting coverage may be so low as to provide limited feedback. Several techniques have been proposed that identify and work with an interesting subset of the design's state machines, but they still require computing the full state graph before projecting it. In this paper we discuss projection directed state exploration, in which a projection from the full graph is found while exploring only the relevant portion of the full graph. Even with this limited exploration, BDD size blowup is still a problem. To deal with this, we have also developed several interactive tools that provide feedback to the designer, and allow them to add hints to help with the exploration.
[1]
Kavita Ravi,et al.
High-density reachability analysis
,
1995,
ICCAD.
[2]
Mark Horowitz,et al.
Architecture validation for processors
,
1995,
Proceedings 22nd Annual International Symposium on Computer Architecture.
[3]
Avner Landver,et al.
Coverage-Directed Test Generation Using Symbolic Techniques
,
1996,
FMCAD.
[4]
Mark Horowitz,et al.
Validation coverage analysis for complex digital designs
,
1996,
ICCAD 1996.
[5]
A. Gupta,et al.
The Stanford FLASH multiprocessor
,
1994,
Proceedings of 21 International Symposium on Computer Architecture.
[6]
Jacob A. Abraham,et al.
Abstraction Techniques for Validation Coverage Analysis and Test Generation
,
1998,
IEEE Trans. Computers.
[7]
Mark Horowitz,et al.
Vex—A CAD toolbox
,
1999,
DAC '99.