Implementation of High-Throughput Digit-Serial Redundant Basis Multipliers over Finite Field

1 (M.Tech-VLSID, Department of Electronics and Communication Engineering,Shri Vishnu Engineering College for Women (Autonomous), India) 2 (Associate Professor,Department of Electronics and Communication Engineering, Shri Vishnu Engineering College for Women (Autonomous), India) __________________________________________________________________________________________ Abstract:In elliptical curve cryptography the redundant basis (RB) multipliers for finite field have achieved immense popularity. The high-throughput multipliers are presented and they utilize redundant representation. In this paper, a novel recursive decomposition algorithm is presented for digit-level RB multiplication to obtain digit-serial implementation. The signal-flow graph (SFG) is extended to obtain the processorspace flow graph (PSFG) and also to acquire the three novel multipliers. Implementation of 10 bit digit-serial RB multipliers is presented in this work. The proposed structures are simulated and synthesized in Xilinx 12.2 using Verilog HDL.