Instruction-Level Program and Processor Modeling
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relationship that allows us to determine how a component will performn before it is implemented.
[1] James W. Rymarczyk. Coding guidelines for pipelined processors , 1982, ASPLOS I.
[2] Alan Jay Smith,et al. Cache Memories , 1982, CSUR.
[3] MAKOTO KOBAYASHI. Dynamic Profile of Instruction Sequences for the IBM System/370 , 1983, IEEE Transactions on Computers.