Reducing the signal Electromigration effects on different logic gates by cell layout optimization

In modern integrated circuits, the Electromigration (EM) effects are not just seen on power delivery networks. EM is also an increasing problem in the internal metal wires of cells, referred as cell-internal signal Electromigration. In this work we present a detailed analysis of the cell-internal signal Electromigration effects considering different logic gates. The lifetime optimization by placing the output pin of the gates is dependent of the output wire shape and the logic of the gate. We are also presenting ways to improve the lifetime of the cells optimizing the cell layout.

[1]  Sachin S. Sapatnekar,et al.  Analyzing the electromigration effects on different metal layers and different wire lengths , 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

[2]  Ki-Don Lee.  Electromigration recovery and short lead effect under bipolar- and unipolar-pulse current , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[3]  C.-K. Hu,et al.  Impact of Cu microstructure on electromigration reliability , 2007, 2007 IEEE International Interconnect Technology Conferencee.

[4]  Osman S. Unsal,et al.  Refueling: Preventing Wire Degradation due to Electromigration , 2008, IEEE Micro.

[5]  Narayanan Vijaykrishnan,et al.  Mitigating electromigration of power supply networks using bidirectional current stress , 2012, GLSVLSI '12.

[6]  Robert C. Aitken,et al.  The past present and future of design-technology co-optimization , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[7]  Chih-Chao Yang,et al.  Electromigration challenges for advanced on-chip Cu interconnects , 2014, Microelectron. Reliab..

[8]  J. Black,et al.  Electromigration—A brief survey and some recent results , 1969 .

[9]  Sachin S. Sapatnekar,et al.  A systematic approach for analyzing and optimizing cell-internal signal electromigration , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[10]  Diana Marculescu,et al.  Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  S. S. Sapatnekar.  What happens when circuits grow old: Aging issues in CMOS design , 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).