Internal self-damping optimization in trench power FETs for high-frequency conversion

The impact of the shield resistance (Rsh) on the waveform ringing and system efficiency is assessed in this work for 30V trench power FETs with shielded-gate (TP-FETs). Two different approaches, named distributed and local Rsh, are extensively investigated by experimental and numerical simulation tools. A layout distributed Rsh emerges as the ultimate solution to maximize the self-damping without penalization on the switching power losses or the product cost. The practical implementation of a TP-FET with distributed Rsh in a 12V-to-1.2V buck converter results in one of the best tradeoffs ever reported between overvoltage (<;3.5V) and peak efficiency (~88%) when operating at 1.3MHz.

[1]  F. Bauwens,et al.  Near-zero gate bouncing in high-frequency converters with shield-plate FETs , 2013, 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC).

[2]  Y. Kawaguchi,et al.  Proposal of the method for high efficiency DC-DC converters and the efficiency limit restricted by silicon properties , 2008, 2008 IEEE Power Electronics Specialists Conference.

[3]  M. Tack,et al.  Improved Trench-Based Power Rectifiers for High-Temperature Smart-Power Applications , 2009, IEEE Electron Device Letters.

[4]  Wonsuk Choi,et al.  New power MOSFET technologies optimized for efficient and reliable telecommunication power system , 2012, 2012 Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC).

[5]  S. Lefebvre,et al.  Influence of the gate internal impedance on losses in a power MOS transistor switching at a high frequency in the ZVS mode , 2002 .

[6]  Keong Kam,et al.  EMC guideline for synchronous buck converter design , 2009, 2009 IEEE International Symposium on Electromagnetic Compatibility.

[7]  Keong Kam,et al.  Quantification of Self-Damping of Power MOSFET in a Synchronous Buck Converter , 2011, IEEE Transactions on Electromagnetic Compatibility.

[8]  H. Akagi,et al.  A System-in-Package (SiP) With Mounted Input Capacitors for Reduced Parasitic Inductances in a Voltage Regulator , 2010, IEEE Transactions on Power Electronics.

[9]  P. Coppens,et al.  A high-speed silicon FET for efficient DC-DC power conversion , 2012, 2012 24th International Symposium on Power Semiconductor Devices and ICs.

[10]  Zhiyang Chen,et al.  Optimizing low side gate resistance for damping phase node ringing of synchronous buck converter , 2012, 2012 IEEE Energy Conversion Congress and Exposition (ECCE).