This paper proposes a noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC), which can be well applied in very high-precision and low-power-applications for Internet of Things (IoTs). An error feedback (EF) through the series connection of capacitors is implemented in the topology, which ensures that the input signal and feedback signal are not attenuated. Therefore, a small gain dynamic amplifier can be used, which has advantages of low power consumption and process-friendly characteristics. Designed in 55-nm CMOS process, the prototype of proposed NS-SAR ADC consumes very low power consumption of 623.6 μW when operating at 40 MS/s, which achieves a peak Schreier FoM of 188 dB with 98-dB signal to noise and distortion ratio (SNDR) at an oversampling ratio (OSR) of 16.