A 4.2mW 10MHz BW 74.4dB SNDR fourth-order CT DSM with second-order digital noise coupling utilizing an 8b SAR ADC

A compact and low-power digital-domain noise coupling technique is proposed for higher-order CT DSM implementation, exploiting the architectural advantage of a SAR ADC and a simple digital filter. With an 8b SAR ADC and a second-order digital noise coupling filter, a prototype fourth-order DSM achieves 74.4dB SNDR for 10MHz BW with an OSR of 16 in a 28nm CMOS, showing an FoMs_dr of 174.5dB.

[1]  Robert Weigel,et al.  A 0.039mm2 inverter-based 1.82mW 68.6dB-SNDR 10MHz-BW CT-ΣΔ-ADC in 65nm CMOS , 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

[2]  Taewook Kim,et al.  A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator , 2015, IEEE Journal of Solid-State Circuits.

[3]  Blazej Nowacki,et al.  15.3 A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[4]  Hae-Seung Lee,et al.  A Continuous-Time Sturdy-MASH $\Delta\Sigma$ Modulator in 28 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.

[5]  Yun Chiu,et al.  15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[6]  Andrew Adams,et al.  A 10/20/30/40 MHz feed-forward FIR DAC continuous-time ΔΣ ADC with robust blocker performance for radio receivers , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[7]  Tien-Yu Lo,et al.  27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).